GlobalFoundries Bets on Physical AI in Dresden With FDX Fusion

GlobalFoundries had two pieces of good news to share from Dresden on October 9, and they tell a single story. The first: the topping-out of its 1.1 billion euro SPRINT fab expansion, completed on schedule and on budget. The second: FDX Fusion, a next generation of its FD-SOI process technology aimed at what the industry is calling physical AI, the chips that go inside robots, cars, drones and industrial equipment rather than data centers.

Europe's chip industry has spent years trying to catch up in the GPU race. GlobalFoundries is now arguing that the race worth winning looks different: lower power, integrated sensing, and communications on the same die as the logic. It is a bet that Europe's industrial base is the customer of the future, and that the future is built in Dresden.

What happened in Dresden

SPRINT is a 1.1 billion euro investment to expand GlobalFoundries' Dresden site, supported by the EU, the German federal government and the Free State of Saxony under the European Chips Act framework. The company expects the expansion to push Dresden's capacity past one million 300mm wafers a year by the end of 2028, which would make it Europe's largest foundry site. The site today employs roughly 3,000 people and runs about 60,000 square meters of cleanroom and laboratory space, at up to 950,000 wafers a year depending on product mix. GlobalFoundries says it has invested more than 10 billion euros in Dresden since 2009.

The topping-out ceremony marks the structural completion of the new construction, with equipment installation to follow while the existing fab keeps running. CEO Tim Breen framed the build as a sovereignty play: "Europe's industrial base depends on chips that have to be available, trusted and built close to the customers who rely on them." GF also plans to offer Europe-only processes and data flows for security-sensitive customers in aerospace, defense and critical infrastructure.

FDX Fusion, explained

FDX Fusion is the next generation of GlobalFoundries' FDX technology, its version of fully depleted silicon-on-insulator (FD-SOI). In an FD-SOI transistor, the channel sits in an ultra-thin silicon film, roughly 70 angstroms, above a buried layer of oxide. Because the film is so thin, the channel is fully depleted by construction, which gives FD-SOI electrostatic advantages similar to FinFET transistors without needing to build the fin. Fewer structures, simpler process.

GF says FDX Fusion targets 7-nanometer-class digital performance with more than twice the density of its first-generation FDX, while integrating analog, mixed-signal, high-frequency RF (up to 0.5 THz ft/fmax), embedded non-volatile memory, in-memory computing and dense logic on the same die. The company calls the target workload STAC: sense, think, act, communicate. The platform aims for logic densities of roughly 14 to 18 million gates per square millimeter while retaining the low leakage and sensor integration that characterize FD-SOI.

Why it skips EUV

The most interesting technical claim is what FDX Fusion does not need: extreme ultraviolet lithography. GlobalFoundries plans to reach 7-nanometer-class performance using advanced argon-fluoride immersion lithography, tighter overlay control, and higher-precision masks from Dresden-based mask maker AMTC. The company expects the process to require about 50 masks, compared with 70 to 80 for advanced 3-nanometer and 2-nanometer FinFET processes. Manfred Horstmann, senior vice president and general manager of GF's European fabs, put it plainly: "For 7-nm-class performance, we don't need EUV."

The key is a strained-silicon substrate being developed with CEA-Leti and Soitec, using a strained 70-angstrom film intended to boost electron mobility by about 25 percent, building on the same consortium that worked on 22FDX, GlobalFoundries' earlier FD-SOI generation. Fewer masks means fewer opportunities for defects, which supports both yield and cost. Per EE Times reporting, GF expects to invest roughly $1 billion over the coming years on FDX Fusion development, including about $250 million for the initial toolset.

Physical AI, not data-center AI

Horstmann drew the strategic line explicitly in an interview with EE Times: "Data center AI is extremely power hungry. Physical AI is a different class of problem, and it needs more than compute. It needs sensors, actuators, communications, low power, and cost efficiency."

The point: the GPU race optimizes for maximum compute density inside a warehouse. Intelligence that moves through the world, in a car, a robot, a drone or an industrial arm, needs to sense and communicate as much as it computes, and it needs to do it on battery power. That is what the STAC framing is about.

The customer list in GF's launch materials reads like Europe's industrial directory. Infineon's Patrick Press said the two companies are strengthening their collaboration to define future 7nm-class FDX Fusion technology for radar and wireless communication products. Executives from Bosch, NXP, Siemens and Tesla, alongside a statement from BMW, pointed to robotics, trusted edge processing and supply-chain resilience for physical AI.

The data center AI train has left the station. But for physical AI, the world is still open.

Why it matters, and what could go wrong

For Europe, this is a different strategy from the one that has delivered disappointment. Rather than chasing TSMC, Intel and Samsung in leading-edge FinFET logic, GF is betting that the next large semiconductor market is differentiated: chips that combine logic with analog, RF and power functions that Europe's automotive and industrial champions actually buy. Dresden's Silicon Saxony cluster, which also hosts Infineon, Bosch and TSMC's ESMC joint venture, is becoming, in Horstmann's phrase, self-propelling: suppliers and design houses follow scale.

The caveats are real, and GF states them. Development of FDX Fusion is planned through the EU's IPCEI Advanced Semiconductor Technologies program, subject to German federal government approval, and that approval has not been granted yet. Demonstrator silicon is targeted for early 2027, an initial process design kit for mid-2027, and manufacturing in 2028. That is a long road with familiar hazards: qualification cycles, customer design wins, and a process window that has to hit on schedule. This is a roadmap, not a product.

Still, the shape of the bet is worth noting. The last decade of European chip policy was largely defensive: subsidies to keep capacity local. FDX Fusion is something more unusual from a European foundry: a bid to define a new market first. If physical AI becomes a distinct semiconductor category the way mobile and data-center AI did, Dresden wants to be where the process technology lives. That is the perspective from which this announcement matters: not as a chip, but as industrial strategy with a cleanroom attached.